1. Field of the Invention
The present invention relates to a semiconductor memory, more particularly a ferroelectric random access memory using a ferroelectric material.
2. Description of the Related Background Art
There is a ferroelectric random access memory (FeRAM) as a semiconductor memory that can record binary data in a nonvolatile manner using the magnitude between two different polarizations of a ferroelectric substance, with taking advantage of a hysteresis characteristic of the ferroelectric substance.
As a capacitor type FeRAM using a ferroelectric material as a capacitor, there are a 1T1C type FeRAM in which one memory cell has one transistor and one ferroelectric capacitor and a 2T2C type FeRAM in which one memory cell has two transistors and two ferroelectric capacitors.
One of the main differences between the 1T1C type FeRAM and the 2T2C type FeRAM is that the 1T1C type FeRAM has a smaller memory cell in size. Thus, a 1T1C memory cell configuration tends to be used when designing FeRAMs, in accordance with increase in memory capacity and miniaturization thereof.
Japanese Patent Application Kokai No. 2004-227663 discloses a ferroelectric memory device having a plurality of cell groups each of which includes first and second reference cells, first and second memory cells, a first reference cell reset circuit, a MOS transistor functioning as a first reference level equalizer, and the like. A reference cell reset driver is provided for each of the plurality of cell groups.
Some semiconductor memories, including FeRAMs, are configured such that a single signal controls reading and writing of data on a plurality of memory cells, in consideration of simultaneous access (reading and writing in the same timing) to a plurality of bits. To produce such an FeRAM that supports the simultaneous access to the plurality of memory cells, for example, a plurality of ferroelectric capacitors are connected to one signal line (plate line) in the FeRAM.
In the FeRAM having a configuration such that the plurality of ferroelectric capacitors are connected to the one plate line, the potential of the plate line is likely to vary for a short time to an unintended level during the reading and writing of data. This is because electric charge held in each of the plurality of ferroelectric capacitors becomes noise during the reading and writing of data, and causes variation in the potential of the plate line. Thereby, the residual polarization value of the ferroelectric capacitors, which represents data of the memory cells, may be reduced, thus deteriorating data retention characteristics.
The deterioration in the data retention characteristics, owing to the reduction in the residual polarization value, becomes not negligible with increase in the number of the memory cells connected to one plate line. Moreover, it is often difficult to suppress the brief variation itself in the potential of the plate line.
The degree of the potential variation in the plate line depends on data written to the memory cells. Thus, the more the number of combinations (worst cases) of data that is the most likely to cause the potential variation in the plate line is, the more the number of screenings of the memory cells and the time for the screenings in a test before shipment are.